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<html xmlns="http://www.w3.org/1999/xhtml"><head><link rel="stylesheet" type="text/css" href="insn.css"/><meta name="generator" content="iform.xsl"/><title>MOVA (tile to vector, four registers)</title></head><body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">MOVA (tile to vector, four registers)</h2><p>Move four ZA tile slices to four vector registers</p>
      <p class="aml">The instruction operates on four consecutive horizontal or vertical slices within a named ZA tile of the specified element size.</p>
      <p class="aml">The consecutive slice numbers within the tile are selected starting from the sum of the slice index register and immediate offset, modulo the number of such elements in a vector. The immediate offset is a multiple of 4 in the range 0 to the number of elements in a 128-bit vector segment minus 4.</p>
      <p class="aml">This instruction is unpredicated.</p>
    <p class="desc">This instruction is used by the alias <a href="mov_mova_mz4_za.html" title="Move four ZA tile slices to four vector registers">MOV (tile to vector, four registers)</a>.</p>
    <p class="desc">
      It has encodings from 4 classes:
      <a href="#iclass_per_byte">8-bit</a>
      , 
      <a href="#iclass_per_halfword">16-bit</a>
      , 
      <a href="#iclass_per_word">32-bit</a>
       and 
      <a href="#iclass_per_doubleword">64-bit</a>
    </p>
    <h3 class="classheading"><a id="iclass_per_byte"/>8-bit<span style="font-size:smaller;"><br/>(FEAT_SME2)
          </span></h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td class="r">0</td><td class="lr">0</td><td class="lr">0</td><td class="l">0</td><td>0</td><td>0</td><td>1</td><td>1</td><td class="r">0</td><td class="lr">V</td><td colspan="2" class="lr">Rs</td><td class="l">0</td><td>0</td><td class="r">1</td><td class="l">0</td><td class="r">0</td><td class="lr">0</td><td colspan="2" class="lr">off2</td><td colspan="3" class="lr">Zd</td><td class="l">0</td><td class="r">0</td></tr><tr class="secondrow"><td colspan="8"/><td class="droppedname">size&lt;1&gt;</td><td class="droppedname">size&lt;0&gt;</td><td colspan="6"/><td/><td colspan="2"/><td colspan="3"/><td colspan="2"/><td/><td colspan="2"/><td colspan="3"/><td colspan="2"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="mova_mz4_za_b1"/><p class="asm-code">MOVA    { <a href="#sa_zd1" title="First destination scalable vector register of a multi-vector sequence (field Zd)">&lt;Zd1&gt;</a>.B-<a href="#sa_zd4" title="Fourth destination scalable vector register of a multi-vector sequence (field Zd)">&lt;Zd4&gt;</a>.B }, ZA0<a href="#sa_hv" title="Horizontal or vertical slice indicator (field &quot;V&quot;) [H,V]">&lt;HV&gt;</a>.B[<a href="#sa_ws" title="32-bit slice index register W12-W15 (field &quot;Rs&quot;)">&lt;Ws&gt;</a>, <a href="#sa_offsf" title="Slice index offset, pointing to first of four consecutive slices, encoded as &quot;off2&quot; field times 4 (field off2)">&lt;offsf&gt;</a>:<a href="#sa_offsl" title="Slice index offset, pointing to last of four consecutive slices, encoded as &quot;off2&quot; field times 4 plus 3 (field off2)">&lt;offsl&gt;</a>]</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSME2.0" title="function: boolean HaveSME2()">HaveSME2</a>() then UNDEFINED;
integer s = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>('011':Rs);
constant integer nreg = 4;
constant integer esize = 8;
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zd:'00');
integer n = 0;
integer offset = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(off2:'00');
boolean vertical = V == '1';</p>
    <h3 class="classheading"><a id="iclass_per_halfword"/>16-bit<span style="font-size:smaller;"><br/>(FEAT_SME2)
          </span></h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td class="r">0</td><td class="lr">0</td><td class="lr">1</td><td class="l">0</td><td>0</td><td>0</td><td>1</td><td>1</td><td class="r">0</td><td class="lr">V</td><td colspan="2" class="lr">Rs</td><td class="l">0</td><td>0</td><td class="r">1</td><td class="l">0</td><td class="r">0</td><td class="lr">0</td><td class="lr">ZAn</td><td class="lr">o1</td><td colspan="3" class="lr">Zd</td><td class="l">0</td><td class="r">0</td></tr><tr class="secondrow"><td colspan="8"/><td class="droppedname">size&lt;1&gt;</td><td class="droppedname">size&lt;0&gt;</td><td colspan="6"/><td/><td colspan="2"/><td colspan="3"/><td colspan="2"/><td/><td/><td/><td colspan="3"/><td colspan="2"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="mova_mz4_za_h1"/><p class="asm-code">MOVA    { <a href="#sa_zd1" title="First destination scalable vector register of a multi-vector sequence (field Zd)">&lt;Zd1&gt;</a>.H-<a href="#sa_zd4" title="Fourth destination scalable vector register of a multi-vector sequence (field Zd)">&lt;Zd4&gt;</a>.H }, <a href="#sa_zan_1" title="ZA tile ZA0-ZA1 to be accessed (field &quot;ZAn&quot;)">&lt;ZAn&gt;</a><a href="#sa_hv" title="Horizontal or vertical slice indicator (field &quot;V&quot;) [H,V]">&lt;HV&gt;</a>.H[<a href="#sa_ws" title="32-bit slice index register W12-W15 (field &quot;Rs&quot;)">&lt;Ws&gt;</a>, <a href="#sa_offsf_2" title="Slice index offset, pointing to first of four consecutive slices, encoded as &quot;o1&quot; field times 4 (field o1)">&lt;offsf&gt;</a>:<a href="#sa_offsl_2" title="Slice index offset, pointing to last of four consecutive slices, encoded as &quot;o1&quot; field times 4 plus 3 (field o1)">&lt;offsl&gt;</a>]</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSME2.0" title="function: boolean HaveSME2()">HaveSME2</a>() then UNDEFINED;
integer s = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>('011':Rs);
constant integer nreg = 4;
constant integer esize = 16;
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zd:'00');
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(ZAn);
integer offset = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(o1:'00');
boolean vertical = V == '1';</p>
    <h3 class="classheading"><a id="iclass_per_word"/>32-bit<span style="font-size:smaller;"><br/>(FEAT_SME2)
          </span></h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td class="r">0</td><td class="lr">1</td><td class="lr">0</td><td class="l">0</td><td>0</td><td>0</td><td>1</td><td>1</td><td class="r">0</td><td class="lr">V</td><td colspan="2" class="lr">Rs</td><td class="l">0</td><td>0</td><td class="r">1</td><td class="l">0</td><td class="r">0</td><td class="lr">0</td><td colspan="2" class="lr">ZAn</td><td colspan="3" class="lr">Zd</td><td class="l">0</td><td class="r">0</td></tr><tr class="secondrow"><td colspan="8"/><td class="droppedname">size&lt;1&gt;</td><td class="droppedname">size&lt;0&gt;</td><td colspan="6"/><td/><td colspan="2"/><td colspan="3"/><td colspan="2"/><td/><td colspan="2"/><td colspan="3"/><td colspan="2"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="mova_mz4_za_w1"/><p class="asm-code">MOVA    { <a href="#sa_zd1" title="First destination scalable vector register of a multi-vector sequence (field Zd)">&lt;Zd1&gt;</a>.S-<a href="#sa_zd4" title="Fourth destination scalable vector register of a multi-vector sequence (field Zd)">&lt;Zd4&gt;</a>.S }, <a href="#sa_zan_2" title="ZA tile ZA0-ZA3 to be accessed (field &quot;ZAn&quot;)">&lt;ZAn&gt;</a><a href="#sa_hv" title="Horizontal or vertical slice indicator (field &quot;V&quot;) [H,V]">&lt;HV&gt;</a>.S[<a href="#sa_ws" title="32-bit slice index register W12-W15 (field &quot;Rs&quot;)">&lt;Ws&gt;</a>, <a href="#sa_offsf_1" title="Slice index offset, pointing to first of four consecutive slices, with implicit value 0">&lt;offsf&gt;</a>:<a href="#sa_offsl_1" title="Slice index offset, pointing to last of four consecutive slices, with implicit value 3">&lt;offsl&gt;</a>]</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSME2.0" title="function: boolean HaveSME2()">HaveSME2</a>() then UNDEFINED;
integer s = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>('011':Rs);
constant integer nreg = 4;
constant integer esize = 32;
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zd:'00');
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(ZAn);
integer offset = 0;
boolean vertical = V == '1';</p>
    <h3 class="classheading"><a id="iclass_per_doubleword"/>64-bit<span style="font-size:smaller;"><br/>(FEAT_SME2)
          </span></h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td class="r">0</td><td class="lr">1</td><td class="lr">1</td><td class="l">0</td><td>0</td><td>0</td><td>1</td><td>1</td><td class="r">0</td><td class="lr">V</td><td colspan="2" class="lr">Rs</td><td class="l">0</td><td>0</td><td class="r">1</td><td class="l">0</td><td class="r">0</td><td colspan="3" class="lr">ZAn</td><td colspan="3" class="lr">Zd</td><td class="l">0</td><td class="r">0</td></tr><tr class="secondrow"><td colspan="8"/><td class="droppedname">size&lt;1&gt;</td><td class="droppedname">size&lt;0&gt;</td><td colspan="6"/><td/><td colspan="2"/><td colspan="3"/><td colspan="2"/><td colspan="3"/><td colspan="3"/><td colspan="2"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="mova_mz4_za_d1"/><p class="asm-code">MOVA    { <a href="#sa_zd1" title="First destination scalable vector register of a multi-vector sequence (field Zd)">&lt;Zd1&gt;</a>.D-<a href="#sa_zd4" title="Fourth destination scalable vector register of a multi-vector sequence (field Zd)">&lt;Zd4&gt;</a>.D }, <a href="#sa_zan" title="ZA tile ZA0-ZA7 to be accessed (field &quot;ZAn&quot;)">&lt;ZAn&gt;</a><a href="#sa_hv" title="Horizontal or vertical slice indicator (field &quot;V&quot;) [H,V]">&lt;HV&gt;</a>.D[<a href="#sa_ws" title="32-bit slice index register W12-W15 (field &quot;Rs&quot;)">&lt;Ws&gt;</a>, <a href="#sa_offsf_1" title="Slice index offset, pointing to first of four consecutive slices, with implicit value 0">&lt;offsf&gt;</a>:<a href="#sa_offsl_1" title="Slice index offset, pointing to last of four consecutive slices, with implicit value 3">&lt;offsl&gt;</a>]</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSME2.0" title="function: boolean HaveSME2()">HaveSME2</a>() then UNDEFINED;
integer s = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>('011':Rs);
constant integer nreg = 4;
constant integer esize = 64;
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zd:'00');
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(ZAn);
integer offset = 0;
boolean vertical = V == '1';</p>
  <div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Zd1&gt;</td><td><a id="sa_zd1"/>
        
          <p class="aml">Is the name of the first destination scalable vector register of a multi-vector sequence, encoded as "Zd" times 4.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Zd4&gt;</td><td><a id="sa_zd4"/>
        
          <p class="aml">Is the name of the fourth destination scalable vector register of a multi-vector sequence, encoded as "Zd" times 4 plus 3.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;ZAn&gt;</td><td><a id="sa_zan_1"/>
        
          
        
        
          <p class="aml">For the 16-bit variant: is the name of the ZA tile ZA0-ZA1 to be accessed, encoded in the "ZAn" field.</p>
        
      </td></tr><tr><td/><td><a id="sa_zan_2"/>
        
          
        
        
          <p class="aml">For the 32-bit variant: is the name of the ZA tile ZA0-ZA3 to be accessed, encoded in the "ZAn" field.</p>
        
      </td></tr><tr><td/><td><a id="sa_zan"/>
        
          
        
        
          <p class="aml">For the 64-bit variant: is the name of the ZA tile ZA0-ZA7 to be accessed, encoded in the "ZAn" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;HV&gt;</td><td><a id="sa_hv"/>
        <p>Is the horizontal or vertical slice indicator, 
      encoded in
      <q>V</q>:
        </p>
        <table class="valuetable">
          
            <thead>
              <tr>
                <th class="bitfield">V</th>
                <th class="symbol">&lt;HV&gt;</th>
              </tr>
            </thead>
            <tbody>
              <tr>
                <td class="bitfield">0</td>
                <td class="symbol">H</td>
              </tr>
              <tr>
                <td class="bitfield">1</td>
                <td class="symbol">V</td>
              </tr>
            </tbody>
          
        </table>
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Ws&gt;</td><td><a id="sa_ws"/>
        
          <p class="aml">Is the 32-bit name of the slice index register W12-W15, encoded in the "Rs" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;offsf&gt;</td><td><a id="sa_offsf"/>
        
          
        
        
          <p class="aml">For the 8-bit variant: is the slice index offset, pointing to first of four consecutive slices, encoded as "off2" field times 4.</p>
        
      </td></tr><tr><td/><td><a id="sa_offsf_2"/>
        
          
        
        
          <p class="aml">For the 16-bit variant: is the slice index offset, pointing to first of four consecutive slices, encoded as "o1" field times 4.</p>
        
      </td></tr><tr><td/><td><a id="sa_offsf_1"/>
        
          <p class="aml">For the 32-bit and 64-bit variant: is the slice index offset, pointing to first of four consecutive slices, with implicit value 0.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;offsl&gt;</td><td><a id="sa_offsl"/>
        
          
        
        
          <p class="aml">For the 8-bit variant: is the slice index offset, pointing to last of four consecutive slices, encoded as "off2" field times 4 plus 3.</p>
        
      </td></tr><tr><td/><td><a id="sa_offsl_2"/>
        
          
        
        
          <p class="aml">For the 16-bit variant: is the slice index offset, pointing to last of four consecutive slices, encoded as "o1" field times 4 plus 3.</p>
        
      </td></tr><tr><td/><td><a id="sa_offsl_1"/>
        
          <p class="aml">For the 32-bit and 64-bit variant: is the slice index offset, pointing to last of four consecutive slices, with implicit value 3.</p>
        
      </td></tr></table></div><div class="syntax-notes"/>
    <div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3>
      <p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckStreamingSVEAndZAEnabled.0" title="function: CheckStreamingSVEAndZAEnabled()">CheckStreamingSVEAndZAEnabled</a>();
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
if nreg == 4 &amp;&amp; esize == 64 &amp;&amp; VL == 128 then UNDEFINED;
integer slices = VL DIV esize;
bits(32) index = <a href="shared_pseudocode.html#impl-aarch64.X.read.2" title="accessor: bits(width) X[integer n, integer width]">X</a>[s, 32];
integer slice = ((<a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(index) - (<a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(index) MOD nreg)) + offset) MOD slices;

for r = 0 to nreg-1
    bits(VL) result = <a href="shared_pseudocode.html#impl-aarch64.ZAslice.read.5" title="accessor: bits(width) ZAslice[integer tile, integer esize, boolean vertical, integer slice, integer width]">ZAslice</a>[n, esize, vertical, slice + r, VL];
    <a href="shared_pseudocode.html#impl-aarch64.Z.write.2" title="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[d + r, VL] = result;</p>
    </div>
  <h3>Operational information</h3><p class="aml">If PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
              <ul><li>
              The values of the data supplied in any of its registers.
            </li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
              <ul><li>
              The values of the data supplied in any of its registers.
            </li><li>The values of the NZCV flags.</li></ul></li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
      Internal version only: isa v33.62, AdvSIMD v29.12, pseudocode v2023-03_rel, sve v2023-03_rc3b
      ; Build timestamp: 2023-03-31T11:36
    </p><p class="copyconf">
      Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved.
      This document is Non-Confidential.
    </p></body></html>
